GB/T 46280.4-2025 Specification for chiplet inerconnection interface—Part 4: Physical layer technical requirements based on 2D package English, Anglais, Englisch, Inglés, えいご
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ICS31.200
CCSL55
National Standard of the People's Republic of China
GB/T46280.4-2025
Specification for chiplet inerconnection interface—Part 4: Physical layer technical requirements based on 2D package
Released on August 19, 2025 Implementation on March 1, 2026
State Administration for Market Regulation, National Standardization Administration
Contents
Preface
Introduction
1 Scope
2 Normative references
3 Terms and Definitions
4 Abbreviations
5 Logical Sublayer
6 Electrical Sublayer Based on 2D Packaging
7 Sideband Path
8 Chiplet Physical Layer Interface
Appendix A (Informative) 2D Package Chip Interconnect Bumpmap Example
A.1 Example 1
A.2 Example 2
Specification for chiplet inerconnection interface—Part 4: Physical layer technical requirements based on 2D package
1 Scope
This document specifies the physical layer technical requirements for the chiplet interconnect interface based on 2D packaging, including initialization and training procedures, physical layer electrical Technical requirements for gas specifications, redundancy mechanisms, interface physical layout, and low-power control.
This document applies to the design, manufacture and application of chiplet interconnect interfaces.
2 Normative references
The contents of the following documents constitute essential provisions of this document through normative references. For dated references, only the version corresponding to that date applies to this document. For undated references, the latest version (including all amendments) applies to this document.
GB/T46280.1 Chiplet Interconnection Interface Specification Part 1: General
3 Terms and Definitions
The terms and definitions defined in GB/T 46280.1 apply to this document.
4 Abbreviations
The following abbreviations apply to this document.
AC: Alternating Current
BIST: Built-in Self-Test
CDM: Charged Device Model
CPIF: ChipletPHYInterface
DC: Direct Current
EMI: Electromagnetic Interference
ICG: Integrated Clock Gating
ICR: Insertion Loss to Crosstalk Ratio
IO: Input/Output port
NRZ: Non-Return to Zero
PHY: Physical layer
PI: Power Integrity
PSXT: Power Sum Crosstalk
RX: Receiver
SDR: Single Data Rate
TX: Transmitter
UI: Unit Interval
5 Logical Sublayer
5.1 Logical Sublayer Functions
In the chiplet interconnection interface architecture specified in GB/T 46280.1, the physical layer is divided into a logical sublayer and an electrical
sublayer. The logical sublayer implements the
following functions: — Data
distribution; — Redundancy
repair; — Scrambling
and descrambling; — Initialization, training, and calibration.
5.2 Data Distribution
Data within each lane is distributed to individual I/O devices for transmission in blocks. Data within each block is transmitted in least significant bit (LSB) order.
The default value for each block is 8 bits; other values are determined through negotiation. Currently, high-bandwidth access supports a block size of 10 bits. For example, with 38 valid I/O devices per lane, the data distribution for each I/O device is shown in Figure 1.
5.3 Redundancy Repair
In order to improve the yield of interconnection, a spare IO can be set in each lane for redundancy repair.
Redundancy repair is an optional function in 2D packaging.
The transmitting end of the backup I/O is denoted as TXRFU, and the receiving end is denoted as
RXRFU. Redundancy repair is performed using a shifting method. For example, in the transmitting direction, the shifting sequence is TX00 ÿ TX01 ÿ TX02 ÿ … N ÿ ÿ TXTXRFU. When a signal interconnection error occurs, the signal is shifted backward, starting from that signal and continuing to TXRFU. All signals in the shifting direction are also rearranged until they terminate at the backup signal. Signal shifting is performed simultaneously at both the transmitting and receiving ends of the same path.
Multiple IOs can also be set for redundancy repair to meet the reliability requirements of specific applications. This can be customized by the user. The redundancy repair shift rules refer to the above shift order requirements.
5.4 Scrambling and Descrambling
Scrambling and descrambling are used to solve the EMI and PI problems caused by multiple IO flipping at the same time when the chip is interconnected. Scrambling and descrambling are optional functions.
This file uses a synchronous scrambling method. The sender uses the scrambling polynomial to generate pseudo-random data and performs XOR processing on the data to obtain
